First Tests in Hall-D

This part describes initial tests of the FDC during cabling as part of the installation in Hall-D

• Low Voltage: The LV crate U2-2-BOT (MAC: 00-50-C2-2D-CE-6F) provides all the bias voltage for all preamp cards (cathode strips and anode wires). The controls and GUIs are based on epics and CSS (control system studio). During installation of the LV cables the current read-backs in the LV GUI are used to verify proper connection (0.4x A for each preamp card).
• Monitoring: To run and monitor the GUIs required for the test a computer is installed in the hall connected to the slow control network. The computer is called "joebesser" (MAC: 00-07-E9-17-F7-A6) it runs a 32 bit redhat5 operating system and will mount the "/group/halld" disk.
• Code: The current programs used to test the ADC pedestals (random trigger) and TDC-cable-preamp chain (with built in pulser) are located under "/group/halld/Subsystems/fdc/daq/linux/code". Below that directory structure the code for running the tests on the readout controller and the code for subsequent analysis of the data.
  • ADC pedestal test: the codes are in ./code/ADCtests/src while the data from the ROC is currently written to ./code/ADCtests/DATA. Once deployed in the Hall the data this may be changed and the data may be written to the halld file system. The functionality of the code is as follows:
    • roc code: src/readout/pedestalTest will run on the ROC. it required at least one command line option -S # where # means the slot number of the ADC to be tested. Running the code without any command line parameter will give the following result:

      ./pedestalTest

      JLAB f125ADC pedestal Tests
      ----------------------------
      usage: pulserTestNew [Options]
             -S #   slot number of ADC to be used in test (default 4)
             -T #   Trigger timing offset default is 30
             -N #   Number of triggers default is 1000