Difference between revisions of "FADC timing"
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The following test was performed: a 3 us long positive block pulse was fed into the fADC. The trigger was setup that this pulse is starts around 1040 ns after the the stop signal in the fADC. The fADC | The following test was performed: a 3 us long positive block pulse was fed into the fADC. The trigger was setup that this pulse is starts around 1040 ns after the the stop signal in the fADC. The fADC | ||
ran at 200 MHz internal clock. | ran at 200 MHz internal clock. | ||
| − | The expected fADC time spectrum is shown in figure | + | The expected fADC time spectrum is shown in figure 1. |
Revision as of 16:42, 1 April 2008
The following test was performed: a 3 us long positive block pulse was fed into the fADC. The trigger was setup that this pulse is starts around 1040 ns after the the stop signal in the fADC. The fADC ran at 200 MHz internal clock. The expected fADC time spectrum is shown in figure 1.
