FADC timing

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The following test was performed: a 3 us long positive block pulse was fed into the fADC and used as a trigger. The trigger was setup so that when the 3 us long pulse is fed into the fADC the stop signal came 1040 ns after the rising edge of the long pulse. The fADC ran at 200 MHz internal clock. The expected fADC time spectrum is shown in figure 1.

figure 1: Expected fADC output. ADC channels as a function of time (ns)

Unfortunately this is not seen in most cases. It turns out that in 1/3 of the cases the rising edge starts at 1025 ns instead of 1040 ns. Also there is a kind of cut off at the end. My theory is that the start pointer returned by the flash ADC is not always the correct one. I already knew that the rising edge can jump 20ns in time but the behavior at the end of the time spectrum was brought to my attention by Gregg Franklin and Diana Parno who is using a similar fADC for the HALL-A polarimeter upgrade and they use different software than I do. An example of a more common spectrum is shown in figure 2.

figure 2: Unexpected fADC output. ADC channels as a function of time (ns)


Here are some statistics:

Event || pulse_start(ns) || pulse_"stop"(ns) (OK means pulse does not stop)

01 1020 2545

02 1025 2045

03 1045 2550

04 1045 2545

05 1040 2550

06 1040 OK

07 1025 2545

08 1045 OK

09 1025 2545

10 1025 2545

11 1045 2555

12 1045 OK

13 1040 OK

14 1040 OK

15 1040 OK

16 1045 2555

17 1025 2545

18 1045 2550

19 1025 2545

20 1040 2555


There is a correlation: I cannot find events which have a signal starting at 1040 and end at 2545 or a start at 1025 and end at 2555. It looks like the stop pointer jumps around, on the other hand for signals that start at 1045 you find endings at 2545,2550,2555, and not ending.


Solution

By reading the manual of the fADC, especially the part concerning event directories, I found a solution. This page tells you that if you have an event directory with the trigger bit set then the last 25 bits of that data word contain the pointer to the next sample address (or the start of your event - i call this start pointer).

The end of that section reads: for more information .... see Next Sample Address: this extra info (5 pages back) tells you that the first two bits of the next sample address (bit 0 and 1) have an extra meaning - they tell you how much the start pointer is off...

bit0 bit1 || meaning

0 0 || all OK

0 1 || 1 sample before stop is not stored + correct start-pointer +1

1 0 || 2 samples before stop not stored + correct start-pointer +2

1 1 || 1 sample after stop stored + correct start-pointer -1

If you apply these corrections you see that eg in case 0 1 that your leading edge is at the correct time but you have a cut off in the last sample (last sample is not stored). In case 1 1 you see a signal in first sample => that is the sample after the stop that is stored. I hope it makes sense. Otherwise -> read the manual.