Proposal on CAEN TDC System Synchronization

From GlueXWiki
Jump to: navigation, search
Date: Fri, 31 Oct 2014 12:39:30 -0400
From: "Mark M. Ito" <>
To: Beni Zihlmann <>,, 
 Aris Arist <>,
 David lawrence <>, Benjamin Raydo <>, 
 Chris Cuevas <>,
 "J. William Gu" <>, Bryan Moffit <>, 
 Paul Eugenio <>
Subject: Re: Sync between the FADC250 and CAEN1290


First, note that this is going to Hall-D, FSU, DAQ, and Fast-Electronics 

Talking to Ben and William, I think we have a proposal for a solution.

1. Increase the TI clock counter from 32 bits to 48 bits. This is a 
software-settable configuration parameter when initializing the TI.

2. Go to new TS firmware that only issues a synch signal that is synched 
to both the 41.67 MHz system clock (24 ns period) used by the CAEN TDCs 
and the 250 MHz clock (4 ns period)) used by the trigger and FADCs. 
William has already written this firmware.

3. Use the TI clock counter to resolve the phase ambiguity of the global 
trigger  (synched to 250 MHz) with respect to the TDC system clock 
(synched to 41.67 MHz), i. e., look at the TI counter modulo 6 to get 
the phase.

4. Do not change the read-out mode of the TDC, i. e., keep the time 
reference to "the beginning of the trigger window" and not change it to 
refer to "the last bunch reset (i. e., global timestamp)". Quotations 
are from Ben's message.

One point of information: we are running the CAEN TDCs from a single 
externally generated clock fanned out to all 6 boards. That is the 41.67 
MHz clock referred to above. The internal clocks are not used.

Comments on the solution:

• Step 2 eliminates the phase ambiguity between the 250 MHz clock and 
the 41.67 MHz clock when the clocks are synched at the beginning of each 
run. Without this change the synch happens at a 6-fold random phase of 
the 41.67 MHz clock and the phase relation of the two clocks would 
change run-to-run.
• Step 1 prevents the TI counter from wrapping around every 17 seconds 
(with 32 bits). The wrap-around time is 13 days for 48 bits. The wrap 
around ruins the phase relationship established by step 1 since the 
ratio of periods is 6:1.
• Step 3 is the method used to shift the TDC time-scale to be the same 
as that of the FADCs. After this correction, we have a single time 
system. There is still the 4 ns ambiguity from the trigger, but that is 
a common offset for TDCs and FADCs.
• The non-change of Step 4 makes the previous comment true. If we made 
that change, it would could be made to work, but we would have different 
a random time shift between for TDCs and FADCs event-to-event.
• We will still put the trigger signal into a spare channel of the last 
TDC board. That by itself should work, and will be a check on this 
solution, or vice-versa if you like.
• A similar discussion should go on for the F1-TDCs.

Do we need a meeting on this?

   -- Mark