OWG meeting 4-Oct-2007

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10:00am Thurs 4-Oct-2007 Cebaf Center F326

1.) dial:

800-377-8846 : US

888-276-7715 : Canada

302-709-8424 : International

2.) enter participant code: 39527048# (remember the "#")


  • ICALEPCS (controls) conference 15-Oct-2007 through 19-Oct-2007
  • Electronics meeting 24-Oct-2007, JLab
  • Collaboration meeting 25-Oct-2007 through 27-Oct-2007, JLab
  • IEEE NSS conference 29-Oct-2007 through 2-Nov-2007

Next Meeting

TBD...next scheduled meeting is during IEEE conference, so we'll see...

New Action Items from this Meeting

  • Form FCAL test subgroup and start meeting to plan next summer's test


Attendees: E.Wolin, David L, Dave A, Graham H, Carl T, Elton S, Elke A, Chris C, Fernando B, Dave D, Walt M. By phone Matt S, Beni Z, Gerard V.

Planning for Electronics meeting - Fernando B

  • Attendees may all be locals, Gerard V and Mitch N may phone in.
  • Dates not settled, perhaps Tues afternoon and Wed morning, or maybe Wed morning and afternoon before the collaboration meeting.
  • Must be done by 4pm so that everyone can go the the JLab Oktoberfest (free food...)!
  • Agenda not settled, but will include brief updates on each module being developed, then a longer round-table discussion of many issues, including trigger and clock distribution, etc.
  • Need 100% design and design specs by May-2008, prior to Lehman (CD-3) review summer 2008, down to the level of cable specs, lengths, and counts.

Status of CNU Trigger R&D - Walter M and Dave D

Walt gave a ppt presention (see link above) that turned into an hour long discussion of many aspects of the Hall D trigger:

  • Walt presented the latest results on simulation of communication using the Xilinx Aurora protocol and hardware (Virtex4).
  • Chris has been working in parallel with the hardware components, developing the crate sum module at JLab.
  • Can run on copper (over backplane, FADC to sum boards in VXS switch slot) or fiber (crate-to-crate, sum boards to trigger processors).
  • Continuous 16 bits @ 250 MHz is needed for board sums in FADC crates.
  • With current hardware will need multiple lanes.
  • One lane supports 3.125 Mb/s at 125 MHz. After overhead drops to 2.5 Mb/s. At proposed frame size will get 2.0 Mb/s. Small frame size desirable for error detection and localization.
  • Internal hiccups or "compensation cycles" require buffering at each end to ensure continuous flow of information. Due to transformation from 16 bit parallel to bit-serial.
  • Use 11 word "pad" to ensure data is always available and minimize latency. Won't start sending until pad is full.
  • Chip/protocol latency 0.5 microsec. Mostly internal with 44-88 nsec due to pad scheme.
  • Max total allowable latency 3.5 microsec due to F1TDC internal buffer size.
  • Absolutely need global timing distribution to keep everything in lock-step.
  • To do: simulate two lanes, add error correction, eventually simulate four lanes.
  • Eventually merge with the JLab effort to implement simulated strategy in real hardware and test.

FCAL Test - Beni Z and Matt S

  • It is time to start planning for the FCAL test next summer or fall, after Jul 2008 shutdown.
  • Requirements and setup should be very similar to those of the 2006 BCAL test.
  • The BCAL test setup was taken apart most of it was given back to the JLab electronics pool. Unfortunately the pool then promptly disappeared. Not sure where everything went, so major scrounging will be needed to resurrect the BCAL setup. Fortunately Chris got some of it. May have to purchase items, so the sooner we know, the better.
  • 8 x 8 FCAL array will be read out by JLab 250 MHz FADC's in VME 64x or VXS,
  • Major goal is detector and FADC testing. Testing VXS crate sum system may be interesting, but not required. Current hardware can handle crate sum from two FADC boards.
  • Will use cart from BCAL test.
  • Will need CLAS tagger crate in DAQ. Thus we will need a TS module and VXI crate, and will have to break into the tagger branch (as before).
  • Need run plan.
  • Need to schedule run time with Hall B and perhaps the PAC.
  • Need trigger plan and diagram.
  • Need list of electronics needed.
  • Need mechanical requirements and installation plan.
  • Need safety and other run documentation.
  • Will use same elog as from BCAL test (see link on DAQ/Online/Controls page).
  • Elliott will collect BCAL test information from 2006.
  • Will be a major topic at upcoming collaboration meeting. Beni will be at JLab all week so some of us will meet before the collaboration meeting.
  • FCAL test working group will be formed. Elliott will be JLab lead and Beni will be IU lead for the test.
  • As with the BCAL test, all JLab Hall D people will need to help, and we'll need many university people on site as well.

Event size study - Elliott W

Almost no time at the end to discuss this.

  • Work in progress.
  • Steering group formed: Elliott, Dave L, Fernando. Held first meeting and will generate "game plan".
  • IU and UConn farms available for running simulations.
  • Eugene's work on Pythia very important here.
  • Will report status at the collaboration meeting.
  • Main questions:
    • How many hits are there from signal, noise, and background?
    • How many bytes-per-hit need to be recorded for each system?