OWG meeting 3-Oct-2008

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Agenda

  • Announcements
  • Review of minutes from 5-Sep-2008 meeting
  • Reschedule online meeting to Wed?
  • Issues from collaboration meeting - all
  • FADC 250 progress - Hai Dong
  • Update on fiber test stand - Beni
  • Other electronics update - Fernando, Chris, Ben, Ed, etc.


Time/Location

3-Oct-2008 2pm CC F326


Announcements

Meeting time changed to alternate Wednesdays at 1:30 pm


Next Meeting

No meeting in two weeks as I'll be out of town

Wed 29-Oct-2008 1:30 pm CC F326


New Action Items from this Meeting

Minutes

Attendees: Elliott W, Simon T, Alex S, David L, Mark I, Elke A, Beni Z, Elton S, Ben R, Jim S, Herun Y, Ed J, Fernando B, Hai D, Chris C, Abhishek G, Vardan G.


Fiber Test Stand - Beni

  • Most dark box parts are here.
  • Chris is helping with the problematic stepper motor. He is purchasing some software from the company.
  • No DAQ problems since the typo in the script was fixed.
  • CAEN HV still tripping occasionally.


Electronics - Fernando, Chris, Ben

  • ACAM rep at JLab 22-Oct 3:30pm to talk about F1 chip and follow-on chips.
  • F1 chip procurement moving along, $220k for 1440 chips incl. 100% yield clause in contract.
  • Few old TI boards left, need to fix a few and perhaps make some more. URegina may need some in a few months.
  • PCI-based TI board mostly working, no requests yet.
  • Test stands being developed by Electronics Group for trigger boards.
  • Boards are being fabricated according to schedule.


FPGA Firmware - Hai

  • See Hai's talk above for many details concerning FPGA programming for the FADC 250 and the CTP boards.
  • Can reprogram FADC EPROM directly via VME. Program version number stored on-board and can be read out.
  • Takes 4 mins to reprogram the EPROM on the FADC 250. Code tested beforehand in simulator.
  • CTP can only be programmed using I2C via the new TI board, as it does not sit in a VME slot.
  • Takes 12 mins to reprogram CTP EPROM.
  • We don't expect to need to reprogram the CTP often, unlike the FADC, where we may install new trigger algorithms with some regularity. Note that frequently changed parameters will be kept in registers that can quickly be changed, ant that this is not the same as reprogramming the FPGA's themselves.
  • VHDL not completed for FADC and CTP yet.
  • Using Altera for VME control since Ed already wrote code for Altera. In other cases using Xilinx FPGA's. Altera probably will not need to be reprogrammed once it is working. Readout algorithms reside in Xilinx chips.
  • Long discussion on how to verify code in EPROM has not been corrupted. Electronics Group will discuss verification strategies.