OWG meeting 29-Feb-2008

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Agenda


Time/Location

2pm Fri 29-Feb-2008 CC F227


Announcements

Next Meeting

Fri 14-mar-2008 2pm CC F326


New Action Items from this Meeting

Minutes

Attendees: Dave A, Elke A, Elton S, Alex S, Vardan G, Carl T, Simon T, Fernando B, Elliott W.


R&D and PED status

  • Fernando reported on the electronics meeting earlier this week. Much progress, but still much left to do, including lots of documentation needed for the May subsystem review (as pre-brief material, etc).
  • Dave A reported on Graham's progress with design and documentation of the EMU (which Graham will present at the next OWG meeting). Drivers are also coming along, documentation on other CODA components, etc.
  • Fernando pointed out we may need additional meetings (on trigger, DAQ, electronics, etc) between now and the May review beyond the every-other-Friday OWG meeting.
  • Elke said she will aim to have the review towards the end of May, if possible (reviewers still need to be identified, etc).


L1 Trigger Algorithm and Related Studies

Alex S. is now running the monte carlo and getting preliminary results:

  • BCAL not working yet, he is working with Richard on this.
  • Eugene's MC has a slight disconnect between data under and over 3 GeV, where the model switches from Pythia to measurements.
  • No EM background included yet.
  • Some digi routines need updating from integrating to flash ADC.
  • Alex showed TOF occupancies, FCAL occupancies, double-hit rates, cluster frequencies, and rates of these vs photon energy with various cuts, how many events survived, etc.
  • Max TOF rate is 24 kHz at 10**8.
  • Using TOF and FCAL in coincidence drops hadronic rates quite a bit compared to either alone. Note that we are designing for 200 kHz trigger rate.
  • Elke pointed out that response of TOF and FCAL to pions needs to be understood.
  • See Alex's presentation for more details. This work in continuing.


Intel-Based Dual-CPU Single Board Computer in VME

Dave Abbott reported on performance studies of an Intel VME dual-CPU board we purchased a few months ago. Currently the halls all use Motorolla PPC SBC's running VxWorks, typically model MV6100:

  • Front-end intelligence is moving from cpu's to FPGA's.
  • 10 kHz max interrupt rate in current cpu's, so cannot interrupt cpu for every event (as the halls do now).
  • VME test stand in DAQ lab has Intel and PPC cpu's, TI card, bus analyzer, FADC, F1TDC, etc.
  • Model is GE FANUX V7865 2GHz Core-Duo w/667 MHz FSB, Dual GBit, USB, 1-3 GB sdram running Linux.
  • Can boot from local disk, network, CF card, etc.
  • Transition module implements many optional features (none of which we likely will need).
  • Has TEMPE chip, capable of 2eSST and other high-speed transfer modes, max VME transfer rates up to 320 GB/s.
  • Our goal is to achieve 160-200 MB/s.
  • Observes 40 us latency from trigger interrupt to execution of user code, compared to 10 us for PPC. This is still much faster than we need in Hall-D.
  • Max 117 MB/s network transfer at 12% of one cpu, compared to 79MB/s at 100% cpu PPC.
  • See his talk for many other comparisons.
  • Current cost is around $4500, compared to $3600 for MV6100 (our budget was based on 80 MV6100 @ $3600 each), but these are new so cost should go down.
  • These are very encouraging results, as there are many advantages to using Linux front-end SBC's.