FADC algorithm

From GlueXWiki
Jump to: navigation, search

A first proposal of a generic algorithm to determine the charge and pedestal (not time). Consider first that the hardware has the following feature:

  • The ADC has 72 channels with 12 first order FPGAs, that means each FPGA handles 6 channels
  • The ADC has a mezzanine part. Every other set of 12 channels is routed to the mezzanine board. So the first 12 channels are on the main board, the second 12 (12-23) are on the mezzanine board the third 12 (24-25) channels are again on the main board and so on. This means that the 6 channels withing an FPGA are neighbouring channels.
  • There is a 13th secondary FPGA that will receive data from the 12 primary FPGAs.

Here we consider first how to determine the pedestal and the charge integral on the primary FPGAs:

  • Because there is a direct correlation between the trigger time (at the ADC) and the first possible time a real signal belonging to the trigger can happen the region before any signal is known and can be used to determine a pedestal. This region should be set/initialized by 2 parameter that can be configured.
  • To determine the charge integral one of two strategies could be followed.
    1. Simply integrate over a predefined time window regardless of the timing of the signal (acts like any old style charge integrating ADC) with the window size and location set by two parameters during initialization like the pedestal ones.
    2. Determine the earliest time/sample over a threshold from any of the 6 input channels to the FPGA and integrate each channel around this found earliest time with a window given by parameters that can be set during initialization.
    • Note that in both cases the pedestal determined previously should be subtracted and maybe even some bit reduction done such that the integral value fits fine withing the 16 bits we allocate for it. In case that a previous signal has its tail significantly inside the region of the pedestal window an offline correction can easily be applied by comparing the current pedestal to the mean pedestal of accumulated events. Or the current pedestal could be compared to a current mean pedestal loaded at start-up and if the current pedestal is too different the mean pedestal value could be used.
  • The values for Pedestal, Integral and Time(not discussed here) for all 6 channels are then shipped to the secondary FPGA that collects all the data from all FPGAs. Note that only those FPGAs have data if at least one of the 6 channels was over threshold in case of option 2.) and all FPGAs have data in case of option 1.)
  • The secondary FPGA applies a threshold (much lower than the first threshold of option 1.)) and discards all data that has integral values below this

threshold. In this way we retain small energy depositions that are below threshold in the first stage(FPGA) and have no timing signal.