FADC Data Format Jan 28, 2014
Location and Time
Room: CC F326-327
Time: 1:30pm-2:30pm
Remote Connection
ESNet: 8542553
(if problems, call phone in conference room: 757-269-6460)
Agenda
- Previous meeting (Jan. 14, 2014)
- Project Schedule
- Quality factors and data format
- CMU timing algorithm
- fADC125 Data Format Specification Document
Minutes
Attendees: David L., Lubomir P., Beni Z., Naomi J.
We discussed the schedule for the FPGA algorithm development. It was confirmed that to our mutual understanding:
- v1 of the FPGA program (straight implementation of current f250 algorithm) would be completed by summer of this year and used in the Fall commissioning run
- A first draft specification document would be produced by March 1st and feedback solicited from the Fast Electronics(FE) and DAQ groups
- This would be for the version 2 or "v2" FPGA program
- A final draft specification document would be produced by April so that the FE Groug can plan the work needed to implement it
- FE and DAQ testing of v2 FPGA program would be completed at least 2 months prior to production running in order for Hall-D physicists to have time to test it in the modules deployed in Hall-D.
David noted that Elton mentioned a conversation he had with Fernando which did not seem consistent with this. David volunteered to speak with Fernando in order to get clarification.
The 12GeV project schedule related to FPGA algorithm development was shown in the form of a spreadsheet Fernando provided. These were activities that had physicist labor attached. It was unclear whether the schedule should be applicable to v1 or v2. David was going to talk to Fernando for clarification.
