FA125 Update March 31, 2015

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No meeting, but a progress report from Cody


It's been going well. I've made some major changes and have the new CDC pulse data
mode going through the new architecture in simulation. 

Here are the highlights: 

1. Removed dual port RAM from processing section and replaced it with a FIFO. This
is a convoluted point but the old version stored header information for every
channel and also shifted through the stored data to create the "combo modes". Now
the header information is pulled from a separate storage element and the correct
format is written at processing. This speeds things up and simplifies the code
greatly. The "data format" section doesn't really have to format very much anymore,
it just handles the daisy chain setup.

2. On the daisy chain I now only use 16 out of 18 bits for data. The old code used
all 18 bits and included the tag words for the VME section (36 bits total to
backend, 32 + 4 on an 18 bit bus). I removed the 4-bit tag words from the front end
and will handle them on the back end. This frees up 2 bits on the bus, one of which
I now use for a source synchronous write enable. This is a win for stability and
routing which should allow me to do #3.

3. Clock everything at 125Mhz. Previously, the daisy chain event builder section to
the processor chip was clocked at 80Mhz. Now both the algorithms and the data
transfer are clocked at 125. This is faster, obviously, but it also removes sections
of code that handled switching clock domains and the tristate write enable. 


What I have left to do is:

1. Implement the rest of the modes. The algorithms already calculate the data I just
need to choose what is written to the FIFO.

2. Add VME registers for new variables, everything is hard coded right now. 

3. Make timing!!! I have the "Processor chip" making timing, but there are a few
hangups on the front end chips. I'm going to wait until I finish the behavioral code
before battling this demon and I might need [Naomi's] help here if the trail leads me to
the upsampling section. It's not too bad though. At this stage it's only three
signals that don't make setup timing and that kind of thing can usually be mitigated
by registering values an extra time (i.e. sacrifice a clock cycle to ease routing
constraints). Also, I still have some cleaning up to do from the old code.

4. Modify VME interface firmware to handle the 32 bit format and mux in tag words. 

5. Test, test, test.


Oh, and right now with 100% occupancy in CDC integral and time mode, sample window
of 100; the time from trigger to end of line storage is 6.7uS. (17% occupancy is
~5uS). This may change some but I think we're in the ballpark.

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