Difference between revisions of "December 17, 2013 Tracking FADC"

Revision as of 17:07, 17 December 2013

Meeting Time and Place

Tuesday December 17, 2013 at 1:30pm At Jefferson Lab, the meeting will be held in F326

Connections

To connect from the outside, please use ESNET

1. ) ESNET: 8542553
   
2. )To connect by telephone, dial:

• You can look up toll-free number at http://www.readytalk.com/intl
• US and Canada: (866)740-1260 (toll free)
  
• International: (303)248-0285 (toll call)
• enter access code followed by the # sign: 3421244#
  

Agenda

1. Announcements
2. FADC Status Update
3. Data formats [[1]]
4. Quality factor(s)

Minutes

Present: Curtis, Naomi, Cody, Ed, Beni, Dave L.

1. FADC Status Update

From Cody:

• full crate tests have been finished with one crate, this involves filling the crate with fadcs and using the SD and fast mode read (A25 bus) to get raw data mode output from all cards using Bryan Moffit's libraries.
• he took Ed's code for the fadc250 VME interface and combined it with Hai's fadc250 code for the BCAL readout, then stripped out the extra parts (reduced 16 channels to 6 for each FPGA) and changed the daisy-chain readout to make it suitable for the fadc125. This is working with raw-mode readout.
• he is now working on the VME programming to enable the firmware to be downloaded onto the FPGAs via the backplane rather than having to use the JTAG cable to each flash one at a time.
• he has made a clock divider down to 40MHz which can be used if necessary, not used so far.

From Naomi:

• Naomi has made a simple pedestal-subtracting threshold crossing finder with interpolation which synthesizes (compiles into a downloadable hardware description for the FPGA) and meets the timing constraint of clock period = 8ns.
• She also has code which upsamples ADC data and then performs a threshold crossing finder, this runs in simulation but only synthesizes if the timing constraints are removed. Still working on this. The code is registered and pipelined but maybe there is something else to improve. Ed said look at multi-cycle timing.

From Ed:

• Hai was planning to rewrite the flash 250 firmware because having the time and integral parts separated was not optimal. The rewrite would enable us to use our preferred data format with time and integral in the same word.
• He expects Hai to start work in the spring and finish in the fall.
• There is a restricte

1. Data formats [[2]]
2. Quality factor(s)
3. Next meeting: Jan 14