Minutes 1-24-2007
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FDC Weekly Meeting
Date: January 24, 2007
Participants: Daniel, Tim, Roger, Fernando, Kim, Simon, Brian, Elke, Chuck, Joe
Next Meeting: Wednesday, January 31, 2007 @ 1:30 p.m.
Contents
Fermilab Trip
- Brian, Simon, Tim, and DSC will travel to FNAL tomorrow to meet with Karen Kephart to discuss the FDC design and the FNAL contribution to the project. - We have prepared a detailed agenda for the visit and this was sent to Karen yesterday. - DSC and Simon have spent some time gathering materials (write-ups and pictures) to take with us. - We have received drawings of the STB layout and wire plane layout from Kim and Roger. Chuck expects to have his mechanical drawings completed early this afternoon and he will give them to Tim. - We will discuss the results from the visit at the next FDC meeting.
Cathode Mechanical Mockups
- Brian has completed a second mechanical cathode mockup using a g10 frame and a multi-piece kapton sheet. Using lessons learned from the first cathode board construction, the results were noticeably improved in the second trial. More lessons were learned that will be incorporated into the third cathode. - An aluminized mylar ground plane is now being stretched out in the full-scale tensioner that was completed by the shop. Brian will complete the first full cathode sandwich construction next week. - Brian has done some flatness measurements using a touch gauge on the completed cathode planes. It looks like things were well within our 100 micron flatness spec. - There have been no new developments through the JLab Survey folks about measuring the cathode flatness. We will shake things up on this front when we get back from FNAL. - DSC has spoken with Dennis Skopik about getting some space in the tent in the EEL clean room. We have been told that we can have some space in the clean room tent sent up for Hall A. Jack Segal is our contact and both Brian and DSC have spoken to him to get this process started. We will probably need to occupy space by the beginning of summer. - Imperfections in the cathode flatness have been noticed due to debris and dust in the machine shop room where the planes are being made. Also the granite table has some rough areas and divots. We will work to either purchase a new granite table or refinish one for the final cathode construction. Brian will negotiate with folks to get a granite table for our use in the clean room. - Fernando will do some calculations to specify the aluminum thickness of our ground planes to ensure that cathode-to-cathode cross talk is below the few percent level. He needs specs for the material so that he can do some calculations. Brian will provide this to him along with a sample of the material being used.
STB Boards
- Kim has updated the drawings of the STBs showing trace layouts for the central board. It is clear that there is essentially no clearance between the HV decoupling capacitors and the wires on either side. DSC proposed the idea of burying the capacitors and perhaps the resistors so that the boards can be stuffed prior to wire winding. This idea was met favorably. More discussion will follow after we talk to Karen Kephart. - Fernando commented that burying the components should not provide any heating issues and that he is not worried about any HV problems provided our design is sound. - DSC will prepare a write-up for Kim detailing the rules of thumb for laying out the STBs. This write-up will include statements on trace width, strip-to-strip separation, ground plane requirements, trace angles, etc. He will complete this work next week.
Cabling Issues
- Joe Beaufait has joined the design group at 0.25 FTE. He is working on plans for laying out and supporting the cables for, among other subsystems, the FDCs. - DSC will meet with Joe to provide him with relevant details and information.
Preamplifier Daughter Board
- Fernando has been having discussions with Gerard Visser regarding the pulser calibration circuitry on the preamp daughter boards as well as on the FADCs and TDCs. - We will have a meeting with Gerard during his visit to JLab next week from 1/29 to 2/1. DSC will organize this meeting.
Shaper/Amplifier Board
- Simon received the shaper/amplifier board from Gerard a few days ago and has connected it into the FDC small-scale prototype readout. So far he has been working to provide Gerard with feedback regarding the tail cancellation and pulse shaping with the device. - Next week he and Gerard will work to make more detailed and quantitative studies and study the timing resolution. - We also discussed the purposes of the shaping done by the ASIC chip and the shaping done by the shaper board. The shaping done by the ASIC chip is primarily for fixing the rise time of all pulses to be the same and to provide some degree of tail cancellation. The shaper boards primarily allow for compatibility of the analog pulse with the input of the FADC and to account for smearing affects induced by the cables that run from the chambers to the electronics. - It seems that the plan is to incorporate Gerard's board into the design of the FADC. However this needs some discussion. It is also important to realize that the performance of Gerard's shaping circuit will be optimized for a particular cable length. Thus we need to fix the length of the cables soon and to ensure that they are all the same length.
dE/dX for the FDC System
- The decision has been made that the FDC system will not have to provide dE/dX information for particle identification. It has been decided that all PID "holes" will be accounted for by the design of the Cherenkov detector.
Minutes prepared by Daniel. Send any comments or corrections along.