Difference between revisions of "JLab Module Configuration in CODA"
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In this wiki page, we attempt to outline how JLab Modules are configured and run within each CODA transition and state. | In this wiki page, we attempt to outline how JLab Modules are configured and run within each CODA transition and state. | ||
− | The following presents a table of the evolving global trigger setting in the EEL Electronics Lab | + | The following presents a table of the evolving global trigger setting in the EEL Electronics Lab. |
+ | {|class="wikitable" | ||
+ | ! CODA Transition | ||
+ | ! Trigger Supervisor Crate | ||
+ | ! Global Trigger Crate | ||
+ | ! Payload Crate | ||
+ | |- | ||
+ | |rowspan="2"|'''Download''' | ||
+ | | <!-- Skip column for TS --> | ||
+ | | <!-- GTP crate --> | ||
+ | '''TI:''' | ||
+ | tiInit() | ||
+ | - tiReload() | ||
+ | - tiDisableVXSSignals() | ||
+ | - tiSetClockSource(1) '''CLOCK SWITCHOVER''' | ||
+ | - FiberMeas() | ||
+ | - Reset IODelay (bit 14) | ||
+ | - Sync auto alignment (bit 11) | ||
+ | - Measure Latency (bit 15) | ||
+ | - Fiber delay auto align (bit 13) | ||
+ | - Set user defaults | ||
+ | tiLoadTriggerTable(0) | ||
+ | tiSetTriggerHoldoff(..) | ||
+ | tiSetSyncDelayWidth(..) | ||
+ | tiSetBlockLevel(..) | ||
+ | tiSetEventFormat(..) | ||
+ | tiSetBlockBufferLevel(..) | ||
+ | |||
+ | tiDisableVXSSignals() | ||
+ | - Disable VXS output Sync and Trig signals | ||
+ | | <!-- Payload crate --> | ||
+ | '''TI:''' | ||
+ | tiInit() | ||
+ | - tiReload() | ||
+ | - tiDisableVXSSignals() | ||
+ | - tiSetClockSource(1) '''CLOCK SWITCHOVER''' | ||
+ | - FiberMeas() | ||
+ | - Reset IODelay (bit 14) | ||
+ | - Sync auto alignment (bit 11) | ||
+ | - Measure Latency (bit 15) | ||
+ | - Fiber delay auto align (bit 13) | ||
+ | - Set user defaults | ||
+ | tiLoadTriggerTable(0) | ||
+ | tiSetTriggerHoldoff(..) | ||
+ | tiSetSyncDelayWidth(..) | ||
+ | tiSetBlockLevel(..) | ||
+ | tiSetEventFormat(..) | ||
+ | tiSetBlockBufferLevel(..) | ||
+ | '''fADC250''' | ||
+ | faInit(...) | ||
+ | - Sync = VXS, Trigger = VXS, Clock = Internal | ||
+ | faSetProcMode(...) | ||
+ | - Set window parameters and mode. | ||
+ | '''SD:''' | ||
+ | sdInit() | ||
+ | sdSetActiveVmeSlots(..) | ||
+ | '''CTP:''' | ||
+ | ctpInit() | ||
+ | - ctpFiberReset() | ||
+ | ctpSetVmeSlotEnableMask(..) | ||
+ | '''TI:''' | ||
+ | tiDisableVXSSignals() | ||
+ | - Disable VXS output Sync and Trig signals | ||
+ | |- | ||
+ | | <!-- TS crate --> | ||
+ | '''TS''': | ||
+ | tsInit() | ||
+ | - Sets user defaults | ||
+ | tsSetTriggerSource(..) | ||
+ | tsSet*Input(..) | ||
+ | - Enables specific inputs | ||
+ | tsSetSyncEventInterval(..) | ||
+ | tsSetBlockLevel(..) | ||
+ | tsLoadTriggerTable() | ||
+ | tsSetTriggerHoldoff(..) | ||
+ | tsSetSyncDelayWidth(..) | ||
+ | tsSetBlockBufferLevel(..) | ||
+ | '''TD''': | ||
+ | tdInit() | ||
+ | - Sets user defaults. | ||
+ | - tdAutoAlignSync() | ||
+ | - - Resets IODELAY (bit 14) | ||
+ | - - Auto Align P0 Sync (bit 11) | ||
+ | tdGSetBlockLevel(..) | ||
+ | tdGSetBlockBufferLevel(..) | ||
+ | tdAddSlave(..) | ||
+ | '''SD''': | ||
+ | sdInit() | ||
+ | sdSetActiveVmeSlots(..) | ||
+ | '''TS''': | ||
+ | tsClockReset() | ||
+ | - Clock250 Resync (0x22) | ||
+ | tsTrigLinkReset() | ||
+ | - Disables trigger link (twice) (0x55), Enables trigger link (0x77) | ||
+ | |- | ||
+ | |rowspan="2"| '''Prestart''' | ||
+ | | <!-- Skip column for TS --> | ||
+ | | <!-- GTP crate --> | ||
+ | '''TI:''' | ||
+ | tiEnableVXSSignals() | ||
+ | - Enable VXS output Sync and Trig signals | ||
+ | tiIntConnect(..) | ||
+ | - Connect trigger routine as interrupt/polling service routine | ||
+ | | <!-- Payload crate --> | ||
+ | '''TI:''' | ||
+ | tiEnableVXSSignals() | ||
+ | - Enable VXS output Sync and Trig signals | ||
+ | '''fADC250:''' | ||
+ | faSetClockSource(..,2) | ||
+ | - Set VXS as clock source | ||
+ | faChanDisable(..,0xffff) | ||
+ | faSetMGTTestMode(..,0) | ||
+ | - Sequence enable | ||
+ | faEnable(..,0,0) | ||
+ | '''TI:''' | ||
+ | tiIntConnect(..) | ||
+ | - Connect trigger routine as interrupt/polling service routine | ||
+ | |- | ||
+ | | <!-- TS crate --> | ||
+ | '''TS:''' | ||
+ | tsSyncReset() | ||
+ | - SyncReset (0xDD) | ||
+ | tsIntConnect(...) | ||
+ | - Connects trigger routine as the interrupt/polling service routine. | ||
+ | - Sets interrupt level and vector. | ||
+ | |- | ||
+ | |rowspan="2"| '''Go''' | ||
+ | | <!-- Skip column for TS --> | ||
+ | | <!-- GTP crate --> | ||
+ | '''TI:''' | ||
+ | tiIntEnable() | ||
+ | - Enable trigger source | ||
+ | | <!-- Payload crate --> | ||
+ | '''fADC250:''' | ||
+ | faChanDisable(..,0x0) | ||
+ | faSetMGTTestMode(..,1) | ||
+ | - Disable sequence | ||
+ | '''TI:''' | ||
+ | tiIntEnable() | ||
+ | - Enable trigger source | ||
+ | |- | ||
+ | | <!-- TS crate --> | ||
+ | '''TS:''' | ||
+ | tsIntEnable(..) | ||
+ | - Enables interrupts or starts polling thread. | ||
+ | - Enables trigger source | ||
+ | |- | ||
+ | |rowspan="2"| '''End''' | ||
+ | | <!-- TS crate --> | ||
+ | '''TS:''' | ||
+ | tsDisableTriggerSource(1) | ||
+ | - Disables all trigger sources | ||
+ | tsIntDisable() | ||
+ | - Disable trigger source | ||
+ | tsIntDisconnect() | ||
+ | - Disconnect trigger routine | ||
+ | |- | ||
+ | | <!-- Skip column for TS --> | ||
+ | | <!-- GTP crate --> | ||
+ | '''TI:''' | ||
+ | tiIntDisable() | ||
+ | - Disable trigger source | ||
+ | tiIntDisconnect() | ||
+ | - Disconnect trigger routine | ||
+ | | <!-- Payload crate --> | ||
+ | '''TI:''' | ||
+ | tiIntDisable() | ||
+ | - Disable trigger source | ||
+ | tiIntDisconnect() | ||
+ | - Disconnect trigger routine | ||
+ | '''fADC250:''' | ||
+ | faDisable(..,0) | ||
+ | |- | ||
+ | |rowspan="2"| '''Pre-Download''' (after '''Reset''', executed prior to '''Download''') | ||
+ | | <!-- TS crate --> | ||
+ | |- | ||
+ | | <!-- Skip column for TS --> | ||
+ | | <!-- GTP crate --> | ||
+ | | <!-- Payload crate --> | ||
+ | '''fADC250:''' | ||
+ | faReset(..,1) | ||
+ | - Resets clock source to Internal | ||
+ | |} |
Latest revision as of 10:30, 9 May 2013
In this wiki page, we attempt to outline how JLab Modules are configured and run within each CODA transition and state.
The following presents a table of the evolving global trigger setting in the EEL Electronics Lab.
CODA Transition | Trigger Supervisor Crate | Global Trigger Crate | Payload Crate |
---|---|---|---|
Download |
TI: tiInit() - tiReload() - tiDisableVXSSignals() - tiSetClockSource(1) CLOCK SWITCHOVER - FiberMeas() - Reset IODelay (bit 14) - Sync auto alignment (bit 11) - Measure Latency (bit 15) - Fiber delay auto align (bit 13) - Set user defaults tiLoadTriggerTable(0) tiSetTriggerHoldoff(..) tiSetSyncDelayWidth(..) tiSetBlockLevel(..) tiSetEventFormat(..) tiSetBlockBufferLevel(..) tiDisableVXSSignals() - Disable VXS output Sync and Trig signals |
TI: tiInit() - tiReload() - tiDisableVXSSignals() - tiSetClockSource(1) CLOCK SWITCHOVER - FiberMeas() - Reset IODelay (bit 14) - Sync auto alignment (bit 11) - Measure Latency (bit 15) - Fiber delay auto align (bit 13) - Set user defaults tiLoadTriggerTable(0) tiSetTriggerHoldoff(..) tiSetSyncDelayWidth(..) tiSetBlockLevel(..) tiSetEventFormat(..) tiSetBlockBufferLevel(..) fADC250 faInit(...) - Sync = VXS, Trigger = VXS, Clock = Internal faSetProcMode(...) - Set window parameters and mode. SD: sdInit() sdSetActiveVmeSlots(..) CTP: ctpInit() - ctpFiberReset() ctpSetVmeSlotEnableMask(..) TI: tiDisableVXSSignals() - Disable VXS output Sync and Trig signals | |
TS: tsInit() - Sets user defaults tsSetTriggerSource(..) tsSet*Input(..) - Enables specific inputs tsSetSyncEventInterval(..) tsSetBlockLevel(..) tsLoadTriggerTable() tsSetTriggerHoldoff(..) tsSetSyncDelayWidth(..) tsSetBlockBufferLevel(..) TD: tdInit() - Sets user defaults. - tdAutoAlignSync() - - Resets IODELAY (bit 14) - - Auto Align P0 Sync (bit 11) tdGSetBlockLevel(..) tdGSetBlockBufferLevel(..) tdAddSlave(..) SD: sdInit() sdSetActiveVmeSlots(..) TS: tsClockReset() - Clock250 Resync (0x22) tsTrigLinkReset() - Disables trigger link (twice) (0x55), Enables trigger link (0x77) | |||
Prestart |
TI: tiEnableVXSSignals() - Enable VXS output Sync and Trig signals tiIntConnect(..) - Connect trigger routine as interrupt/polling service routine |
TI: tiEnableVXSSignals() - Enable VXS output Sync and Trig signals fADC250: faSetClockSource(..,2) - Set VXS as clock source faChanDisable(..,0xffff) faSetMGTTestMode(..,0) - Sequence enable faEnable(..,0,0) TI: tiIntConnect(..) - Connect trigger routine as interrupt/polling service routine | |
TS: tsSyncReset() - SyncReset (0xDD) tsIntConnect(...) - Connects trigger routine as the interrupt/polling service routine. - Sets interrupt level and vector. | |||
Go |
TI: tiIntEnable() - Enable trigger source |
fADC250: faChanDisable(..,0x0) faSetMGTTestMode(..,1) - Disable sequence TI: tiIntEnable() - Enable trigger source | |
TS: tsIntEnable(..) - Enables interrupts or starts polling thread. - Enables trigger source | |||
End |
TS: tsDisableTriggerSource(1) - Disables all trigger sources tsIntDisable() - Disable trigger source tsIntDisconnect() - Disconnect trigger routine | ||
TI: tiIntDisable() - Disable trigger source tiIntDisconnect() - Disconnect trigger routine |
TI: tiIntDisable() - Disable trigger source tiIntDisconnect() - Disconnect trigger routine fADC250: faDisable(..,0) | ||
Pre-Download (after Reset, executed prior to Download) | |||
fADC250: faReset(..,1) - Resets clock source to Internal |