Difference between revisions of "Bill's to do list"
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==2020 Summer DIRC To-do List== | ==2020 Summer DIRC To-do List== | ||
# Hall work: | # Hall work: | ||
− | #* Water level sensor installation | + | #* Water level sensor installation |
− | #* Darkening leak check | + | #**Total: 2 days. 1 day testing + 1 day installation |
− | #* Modification on vent exit to reduce FPGA temperature | + | #* Darkening leak check |
− | #* DIRC Diffuser seal issue | + | #** Total: 1 day |
+ | #* Modification on vent exit to reduce FPGA temperature | ||
+ | #** Total: 3 days. 1 day diagnose, 1 day test and 1 day installation. Excluding time for designing time. | ||
+ | #* DIRC Diffuser seal issue | ||
+ | #** Total: 2 days. 1 day test and 1 day installation. Excluding time for water seal test | ||
+ | #* Contaminated mirror replacement in north upper OB | ||
+ | #** Total: 1 days. Uninstall + Disassembly: 1 day; mirror removal + setting up clean area, mirror gluing+ curing: 3 days; silicone seal + cleaning + assembly: 1 days; installation: 1 day. Excluding time for water seal test | ||
+ | #* Inspect the south lower OB | ||
+ | #** 1 day | ||
+ | #** If mirror problem, adding 6 more days for mirror replacement. | ||
+ | # Non Hall Work: | ||
+ | #* Testing spare DIRC modules | ||
#* Control and operation | #* Control and operation | ||
#** Alarm modification strategy | #** Alarm modification strategy | ||
Line 44: | Line 55: | ||
#** Dis-entangle DIRC interlock and interlock reset from FCAL and CCOM | #** Dis-entangle DIRC interlock and interlock reset from FCAL and CCOM | ||
#** Individual (stand alone) SiPM TDA offset | #** Individual (stand alone) SiPM TDA offset | ||
− | |||
− | |||
#* Tile FPGA voltage regulation issue. | #* Tile FPGA voltage regulation issue. | ||
− | # | + | #* Recover loan-out (Duke SOLID group) MOROC chips |
− | + |
Latest revision as of 13:49, 10 April 2020
2018
- Priority list:
- Laser alignment and generating mis-alignment table (Bill, Andrew). ✓
- Feedthrough opening angle measurement and fish tank (Bill, Fernando). ✓
- Light monitors testing and mounting (Bill, Keith). ✓
- DIRC module cabling strategy (Bill/Andrew). ✓
- Hole opening on the backplate (Keith). ✓
- Hole opening on the of the PMT mounting plate (Tim, Keith, Bobby). ✓
- Plastic bolts and screws for the FPGA board. (Chris) ✓
- Recover PMT #9 and 10 and perform test ✓
- Spare micro-BNC cable for the big box. (Omen) ✓
- Cleaning of the mirrors. (Greg, Keith) ✓
- Remarking and repositioning the Fiber cable label. (Fernando/Chris) ✓
- PMT mounting plate spacer (Bobby) ✓
- Installation tray. (Mark/Keith) ✓
- Installation spacer. (Bobby) ✓
2019
- Temperature reduction for the DIRC FPGAs.
- Water quality setup, 3D printing the box.
- Darkening. ✓
- Uni-strut reinforcement for the distribution boxes. ✓
- Airflow sensor ✓
- Opening both DIRC boxes in January:
- Check mirror quality ✓
- Check anodize quality ✓
- Check water tightness of the diffuser assembly. ✓
- North Box:
- Check corner interference. ✓
- Silicone around the wielding spot. ✓
- South Box:
- Check the chipped corner water seal for both spots
2020 Summer DIRC To-do List
- Hall work:
- Water level sensor installation
- Total: 2 days. 1 day testing + 1 day installation
- Darkening leak check
- Total: 1 day
- Modification on vent exit to reduce FPGA temperature
- Total: 3 days. 1 day diagnose, 1 day test and 1 day installation. Excluding time for designing time.
- DIRC Diffuser seal issue
- Total: 2 days. 1 day test and 1 day installation. Excluding time for water seal test
- Contaminated mirror replacement in north upper OB
- Total: 1 days. Uninstall + Disassembly: 1 day; mirror removal + setting up clean area, mirror gluing+ curing: 3 days; silicone seal + cleaning + assembly: 1 days; installation: 1 day. Excluding time for water seal test
- Inspect the south lower OB
- 1 day
- If mirror problem, adding 6 more days for mirror replacement.
- Water level sensor installation
- Non Hall Work:
- Testing spare DIRC modules
- Control and operation
- Alarm modification strategy
- Resolving (double checking) DIRC hole in occupancy before run starts
- Dis-entangle DIRC interlock and interlock reset from FCAL and CCOM
- Individual (stand alone) SiPM TDA offset
- Tile FPGA voltage regulation issue.
- Recover loan-out (Duke SOLID group) MOROC chips