Event size

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Introduction

The average event size determines backplane bandwidth requirements, network bandwidth requiremens, number of modules per crate, and many other things. Fortunatly the DAQ system is highly modular and scalable, so accomodating even a doubling of the event size should be no problem. I.e. more crates may be needed, and perhaps a faster RAID system, but no change in architechture would be needed. See the discussion in the minutes from the 29-Aug-2007 Online Working Group meeting dedicated to this topic.


Steering Committee

One of the results of the meeting was the formation of a steering committee to oversee the effort to understand the event size. Members are Elliott W, David L, and Fernando B, representing the online, offline, and electronics efforts.

Notes from first meeting 25-Sep-2007:

  • need to undersand board occupancies, average event size/rate, and burst (worst case) size/rate
  • need to understand header sizes and what data the boards generate if there are no hits
    • minimize in production boards and for production running (vs debug modes)
    • header words can be removed at many stages: on board, by ROC, by EB, in farm, and by ER
      • need to understand data rates at each stage
    • board should not put out chip-specific information, only board-level information (in production mode)
    • possible ways to recognize that all boards are reporting
      • header/trailer words for each event
      • ROC-generated bit mask for each event
      • error flags if a board did not report, no data generated
      • check periodically (not each event)
      • others?
  • event sources
    • will use renormalized (scaled) Pythia to generate hadronic events
      • See Alex's report on comparision betweeed renormalized Pythia and published data
    • will use Geant to generate EM backgrounds (mostly pair production) from the coherent brem beam
    • hadronic events can pass the trigger, or be accidental background for another trigger,
    • multiple events may pass trigger even though individually they wouldn't
    • need to be careful about time cuts, out of time tracks, tracks from previous event, etc.
  • need backgrounds from full energy range of incident photons, including low energy photons
  • need to run MC with latest geometry, or at least one with a reasonable upper limit on material
  • need to better simulate Level 1 trigger algorithm
    • can be applied to generated events or after simulation
  • Dave estimates we need the following computing/simulation time
    • event generation goes quickly, perhaps only a few hours
    • 1 week simulation hadronic Pythia events, both triggers and accidental
    • 1 week simulation Geant EM background events
  • need to understand bytes per hit for all detector/electronics combinations
    • is timing needed
    • adc + tdc vs adc only


Game Plan and Status

As of 4-Oct-2007:

  • L1 algorithm - Dave L will talk with Dave D.
  • Event generator - Dave L will talk with Eugene.
  • Time windows - Elliott will talk with Elton and other detector folks.
  • Detector geometry - Elliott will talk with Richard.
  • Defining hist set - Dave L and Elliott will go over what exists and what else is needed.
  • Running HDGeant - hope to get help from Richard, Matt, Mark, etc.
  • Number of bytes-per-hit - Fernando will review electronics, detectors, etc. He also will check if noise will be significant.


As of 5-Dec-2007:

  • New collaborators (Chinese) will redo L1 rejection algorithm study.
  • Eugene has extended Pythia to low energies, and has parameterized even lower energy photon interactions.
  • Richard is updating detector geometry.
  • Eugene will run simulations, including EM background simulation. Will need L1 algorithm and time windows.
  • Ed and Fernando say that header words will be kept to a minimum, and should not be a problem.
  • Number of bytes-per-hit is still not settled.


As of 7-Jan-2008:

  • Eugene almost completed low-energy full hadronic simulation (Pythia + "cocktail of reactions")